? semiconductor components industries, llc, 2015 february, 2015 ? rev. p3 1 publication order number: p3p623s00/d P3P623S00B, p3p623s00e product preview timing-safe peak emi reduction ic functional description P3P623S00B/e is a versatile, 3.3 v zero?delay buffer designed to distribute t iming?safe clocks with peak emi reduction. P3P623S00B is an eight?pin version, accepts one reference input and drives out one low?skew t iming?safe clock. p3p623s00e accepts one reference input and drives out eight low?skew timing?safe clocks. P3P623S00B/e has an ss% that selects 2 different deviation and associated input?output skew (t skew ). refer to the spread spectrum control and input?output skew table for details. p3p623s00e has a clkout for adjusting the input?output clock delay, depending upon the value of capacitor connected at this pin to gnd. P3P623S00B/e operates from a 3.3 v supply and is available in two different packages, as shown in the ordering information table. application P3P623S00B/e is tar geted for use in displays and memory interface systems. general features ? clock distribution with timing?safe peak emi reduction ? input frequency range: 20 mhz ? 50 mhz ? 2 different spread selection options ? spread spectrum can be turned on/off ? external input?output delay control option ? supply voltage: 3.3 v 0.3 v ? P3P623S00B: 8 pin soic p3p623s00e: 16 pin tssop ? the first true drop?in solution ? these devices are pb?free, halogen free/bfr free and are rohs compliant this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. www. onsemi.com pin configuration see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information tssop?16 case 948an clkin nc 1 2 3 4 5 6 7 8 gnd sson vdd nc ss% clkou t P3P623S00B 2 13 15 16 10 11 12 clkout 6 clkout 7 clkout 4 clkout 5 vdd clkout dly_ctrl gnd ss% vdd gnd clkout2 clkout3 clkout1 1 3 4 5 6 7 8 clkin 9 sson p3p623s00e 14 1 8 soic?8 nb case 751
P3P623S00B, p3p623s00e www. onsemi.com 2 figure 1. general block diagram pll clkin vdd dly_ctrl ss% gnd sson clkout(s)* (timing?safe) *for p3p623s00e ? 8 clkouts spread spectrum frequency generation the clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. analysis shows that a square wave is composed of fundamental frequency and harmonics. the fundamental frequency and harmonics generate the energy peaks that become the source of emi. regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. in fact, the peak level allowed decreases as the frequency increases. the standard methods of reducing emi are to use shielding, filtering, multi?layer pcbs, etc. these methods are expensive. spread spectrum clocking reduces the peak energy by reducing the q factor of the clock. this is done by slowly modulating the clock frequency. the P3P623S00B/e uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. with center modulation, the average frequency is the same as the unmodulated frequency and there is no performance degradation. zero delay and skew control all outputs should be uniformly loaded to achieve zero delay betwe en input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input?output delay. for applications requiring zero input?output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero input?output delay. timing?safe technology timing?safe technology is the ability to modulate a clock source with spread spectrum technology and maintain synchronization with any associated data path. table 1. pin description for P3P623S00B pin # pin name type description 1 clkin (note 1) input external reference clock input, 5 v tolerant input 2 nc no connect 3 ss% (note 3) input spread spectrum selection. has an internal pull up resistor 4 gnd power ground 5 sson (note 3) input spread spectrum enable and disable option. when sson is high, the spread spectrum is enabled and when low, it turns off the spread spectrum. has an internal pull up resistor 6 clkout (note 2) output buffered clock output (note 4) 7 vdd power 3.3 v supply 8 nc no connect 1. weak pull down 2. weak pull?down on all outputs 3. weak pull?up on these inputs 4. buffered clock output is timing?safe
P3P623S00B, p3p623s00e www. onsemi.com 3 table 2. pin description for p3p623s00e pin # pin name type description 1 clkin (note 1) input external reference clock input, 5 v tolerant input 2 clkout1 (note 2) output buffered clock output (note 4) 3 v dd power 3.3 v supply 4 ss% (note 3) input spread spectrum selection. refer to the spread spectrum control and input?output skew table. has an internal pull up resistor. 5 gnd power ground 6 clkout2 (note 2) output buffered clock output (note 4) 7 clkout3 (note 2) output buffered clock output (note 4) 8 dly_ctrl output external input?output delay control 9 sson (note 3) input spread spectrum enable and disable option. when sson is high, the spread spectrum is enabled and when low, it turns off the spread spectrum. has an internal pull up resistor. 10 clkout4 (note 2) output buffered clock output (note 4) 11 clkout5 (note 2) output buffered clock output (note 4) 12 gnd power ground 13 v dd power 3.3 v supply 14 clkout6 (note 2) output buffered clock output (note 4) 15 clkout7 (note 2) output buffered clock output (note 4) 16 clkout (note 2) output buffered clock output (note 4) 1. weak pull down 2. weak pull?down on all outputs 3. weak pull?up on these inputs 4. buffered clock output is timing?safe table 3. spread spectrum control and input?output skew device input frequency ss % deviation input?output skew ( t skew ) P3P623S00B/e 32 mhz 0 0.25% 0.125 1 0.50% 0.25 table 4. absolute maximum ratings symbol parameter rating unit vdd supply voltage to ground potential ?0.5 to +4.6 v vin dc input voltage (clkin) ?0.5 to +7 t stg storage temperature ?65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22? a114?b) 2 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
P3P623S00B, p3p623s00e www. onsemi.com 4 table 5. operating conditions parameter description min max unit vdd operating voltage 3.0 3.6 v t a operating temperature (ambient temperature) ?40 +85 c c l load capacitance 30 pf c in input capacitance 7 pf table 6. electrical characteristics symbol parameter conditions min typ max units v il input low voltage (note 5) 0.8 v v ih input high voltage (note 5) 2.0 v i il input low current v in = 0 v 50 a i ih input high current v in = vdd 100 a v ol output low voltage (note 6) i ol = 8 ma 0.4 v v oh output high voltage (note 6) i oh = ?8 ma 2.4 v i dd supply current unloaded outputs 27 ma z o output impedance 23 5. clkin input has a threshold voltage of vdd/2 6. parameter is guaranteed by design and characterization. not 100% tested in production. table 7. switching characteristics parameter test conditions min typ max units input frequency 20 50 mhz output frequency 30 pf load 20 50 mhz duty cycle (notes 7, 8) = (t 2 / t 1 ) x 100 measured at vdd/2 40 50 60 % output rise time (notes 7, 8) measured between 0.8 v and 2.0 v 2.5 ns output fall time (notes 7, 8) measured between 2.0 v and 0.8 v 2.5 ns output?to?output skew (notes 7, 8) all outputs equally loaded with ssoff 250 ps delay, clkin rising edge to clkout rising edge (note 8) measured at vdd/2 with ssoff 350 ps device?to?device skew (note 8) measured at vdd/2 on the clkout pins of the device 700 ps cycle?to?cycle jitter (notes 7, 8) loaded outputs 250 ps pll lock time (note 8) stable power supply, valid clock presen- ted on clkin pin 1.0 ms 7. all parameters specified with 30 pf loaded outputs. 8. parameter is guaranteed by design and characterization. not 100% tested in production.
P3P623S00B, p3p623s00e www. onsemi.com 5 switching waveforms figure 2. duty cycle timing figure 3. all outputs rise/fall time figure 4. output?output skew figure 5. input?output propagation delay figure 6. device?device skew output output 0.8 v 2 v 0.8 v 2 v output output output input t 2 t 1 t 3 t 4 t 5 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 t 6 clkout, device 2 clkout, device 1 v dd /2 v dd /2 t 7
P3P623S00B, p3p623s00e www. onsemi.com 6 figure 7. input?output skew t skew ? one clock cycle n=1 t skew + t skew represents input?output skew when spread spectrum is on input clock 32 mhz, translates in to (1/32 mhz)*0.125 = 3.90 ns timing?safe output input for example, t skew = 0.125 for an figure 8. test circuit v dd gnd load output 0.1uf +3.3v 0.1uf +3.3v v dd clkout figure 9. typical example of timing?safe waveform input clkout with ssoff input timing?safe clkout
P3P623S00B, p3p623s00e www. onsemi.com 7 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
P3P623S00B, p3p623s00e www. onsemi.com 8 package dimensions tssop16, 4.4x5 case 948an issue o pin#1 identification 1 a1 a2 d top view side view end view e e1 b l1 c l a symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.85 0.19 0.13 0.45 4.90 6.30 4.30 0.65 bsc 1.00 ref 1.10 0.15 0.95 0.30 0.20 0.75 5.10 6.50 4.50 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. e
P3P623S00B, p3p623s00e www. onsemi.com 9 table 8. ordering information part number marking package type temperature P3P623S00Bg?08sr ado 8?pin 150?mil soic ? tape & reel, green 0 c to +70 c P3P623S00Bg?08tr ado 8?pin 4.4 mm tssop ? tape & reel, green 0 c to +70 c p3i623s00bg?08tr adp 8?pin 4.4 mm tssop ? tape & reel, green ?40 c to +85 c p3p623s00eg?16tr p623 s00e 16?pin tssop ? tape & reel, green 0 c to +70 c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 p3p623s00/d timing safe is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
|
